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Clock and Data Recovery Products

Bellcore specifications require certain performance characteristics for products interfacing with the public SONET network in terms of jitter transfer, jitter tolerance, jitter peaking, and clock stability. When designing systems that will interface on these networks, it is important to specify CDR parts which meet all of the Bellcore specifications. Since performance tradeoffs exist between these specifications, a part which claims to meet the jitter transfer characteristics for example may not meet other characteristics such as jitter peaking. In addition, there may be other attributes which are required in a particular system which are not specified by the Bellcore specifications. An example of this is acquisition time. Most manufacturers require that the CDR part acquire the signal in one frame of data, or 125 uS at 155.52 MHz. A first order PLL can meet the specified Bellcore jitter transfer characteristics, but only at the expense of an extraordinarily long acquisition time. Although not explicitly specified by Bellcore, the real system may well require a faster acquisition time than the simple PLL can provide. As will be seen, enhancements can be made to PLL based CDR parts to enhance performance in certain areas however.

Approaches to CDR
Any basic filtering element can be used to recover a clock signal, but for frequencies up to about 2.5 GHz, the three basic approaches to accomplish the CDR function are 1) SAW filter, 2) PLL with VCXO and 3) all silicon VCO. Each of these approaches will be discussed in more detail later.

SONET Specifications
Prior to the advent of SONET, each particular equipment manufacturer configured their equipment uniquely. The SONET standards provide a consistent framework for the design of data transmission systems. Being a synchronous system, jitter generation and transfer criteria is critical to controlling jitter accumulation, particularly within SONET "islands". SONET requirements for the clock and data recovery function have been delineated in both Bellcore TR-NWT-000499 and ITU-T G.958.

Jitter performance requirements of both documents are specified in terms of 1) jitter transfer, 2) jitter tolerance and 3) jitter generation. Jitter transfer requirements effectively specify a 1st order filter (ie. -20 dB/decade rolloff) configuration with a specified jitter gain or peaking. In the case of PLL’s, this corresponds to the loop dynamics, while in SAW filter parts jitter gain corresponds directly to the SAW filter ripple. Jitter peaking is a key requirement since jitter will exponentially accumulate in a SONET network as the peaking begins to exceed 0.1 dB.

Jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal which causes a 1 dB power penalty. Note that ITU-T recommendation G.958 also allows a type "B" SONET regenerator. The jitter tolerance specifications for the type "B" part are not as stringent. Consequently, the jitter transfer bandwidth is also correspondingly narrower. The type "B" specifications are generally associated with PLL based parts, while SAW filters are commonly used for the more stringent type "A" specifications. Jitter could potentially become a problem with devices which meet the type "A" transfer characteristics are intermixed with devices which can only accommodate the type "B" jitter tolerance requirements. This condition is under further study by the standards organizations.

The third criterion is jitter generation. This requirement essentially specified the amount of jitter which can be added to the signal, with no jitter present on the input. It is especially important when selecting parts to ensure that devices meet all three requirements, since a less expensive part can be easily designed which only meets a portion of the requirements. Both the Bellcore and ITU-T specifications specify that jitter generation cannot exceed 0.01 UI, or 16 ps at STM-3.

SAW filter based CDR
With their inherent small size, high "Q", and excellent repeatability, SAW filters are well suited to the task of CDR. A block diagram of a typical SAW based CDR such as VI’s TRU-600.

Because theoretically no energy exists at the clock frequency with NRZ data, incoming data must pass through a nonlinear element to generate energy at the clock frequency. Being a very narrowband device (i.e. high Q), the SAW filter extracts the clock signal from the other frequencies. All that remains to recover the data is to use the clock to gate the flip-flop. It is essential that the phase shift through the SAW filter path be properly timed with the data to minimize the BER. Additional amplification is generally necessary to ensure that the SAW filter is being driven at the proper level, since the energy at the clock frequency is a strong function of the data density. One important advantage of this approach is that since the SAW is a passive device, no additional jitter is introduced by the filter. With careful design of the entire module, the jitter added by the CDR part can be very low. Jitter for the TRU-600 is typically 10 ps rms at 155.52 MHz. Since the clock signal only exists in the presence of data, an external clock is generally used in conjunction with SAW based CDR’s. Simple logic circuitry can be added to switch in the external clock in the absence of data, as shown in Figure 2. This is particularly useful for applications which require the use of a higher stability clock than what can be derived from a simple crystal oscillator. For example, the STRATUM III frequency stability of ± 4.6 ppm is commonly encountered in SONET applications. In this case, an external TCXO is necessary to maintain the frequency stability over temperature and time.

The TRU-600 meets all performance characteristics as specified by Bellcore and CCITT including jitter tolerance, transfer and accommodation. It is packaged in a 28 pin ceramic SMT package.

PLL Based CDR with VCXO
PLL’s are also commonly used to accomplish the CDR function. To achieve the necessary performance characteristics in terms of jitter suppression along with reasonable acquisition times, a crystal controlled VCXO is usually used for the loop oscillator.

Note that with this approach the clock is still available in the absence of data. Since both Bellcore and ITU-T specifications require a frequency stability of ± 20 PPM for SONET products, the oscillator must be of a fairly high quality to maintain this accuracy when the effects of both temperature and aging are taken into account. Since aging on crystal oscillators can be several ppm per year on lower quality oscillators, a device with a specified initial stability of ± 20 ppm may drift out of tolerance in a few years of use.

In a similar fashion to SAW filters, PLL’s can exhibit significant jitter peaking when cascading devices. It is critically important that the loop filter be properly selected to minimize this effect. In addition, PLL’s can be relatively sensitive to power supply noise. This can be particularly troublesome if, for example, the switching frequencies of power supplies in a distributed network are at similar frequencies. Many enhancements to the simple second order PLL can be designed to achieve certain performance characteristics. A few of these parts are discussed below.

The TRU-050 is a PLL based CDR which allows the user to set the loop bandwidth with external resistors/capacitors. By incorporating the PLL components into a single IC, the TRU-050 is an ideal part to minimize size and cost.

The TRU-050 is available in a ceramic 16 pin DIP with through-hole leads or surface mount with gull-wing lead configuration.

The SCRM 155 is an example of an enhanced PLL based device.

Adding the phase shifter significantly improves both the acquisition time and the ability of the part to acquire or maintain lock in the presence of jitter (jitter tolerance). It is available in a hermetically sealed metal DIP, or in a plastic package utilizing chip-on-board technology.

Other parts based on PLL technology include the SCRM-622 These devices are PLL based, but do not include the phase aligner.